/*
 * Copyright (C) 2020  Max Regan
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "Bsp/macros.h"
#include "Mcu.h"


void SystemInit()
{
    /**
     * Use the MSI for the system clock, and disable all other clocks.
     */

#if defined(STM32L0XX)
    // STM32L0
    SET_TO(RCC->ICSCR,
           RCC_ICSCR_MSIRANGE,
           RCC_ICSCR_MSIRANGE_6);
#elif defined(STM32L4XX)
    // STM32L4
    SET_TO(RCC->CR,
           RCC_CR_MSIRANGE,
           RCC_CR_MSIRANGE_6);
#else
#error "Unsupported device type"
#endif

    /*!< Set MSION bit. Set by hardware to force the MSI oscillator ON
     * when exiting from Stop or Standby mode, or in case of a failure
     * of the HSE oscillator used directly or indirectly as system
     * clock. This bit cannot be cleared if the MSI is used as system
     * clock. */
    SET(RCC->CR,
        RCC_CR_MSION);

    /*!< Set internal representation of clock frequency to 4MHz */
    // system_clk_freq = 4u << 22;

    /*!< Reset
     * SW[1:0] (use MSI oscillator as system clock),
     * HPRE[3:0] (do not divide AHB clock in prescaler) ,
     * PPRE1[2:0] (do not divide APB low-speed clock)
     * PPRE2[2:0] (do not divide APB high-speed clock),
     * MCOSEL[2:0] (disable MCO clock),
     * MCOPRE[2:0] (disable MCO prescaler) */
    CLR(RCC->CFGR,
          RCC_CFGR_SW | ~RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 |
          RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE);

    /*!< Reset HSEBYP bit (disable HSE bypass) */
    CLR(RCC->CR,
          RCC_CR_HSEBYP);

    /*!< Reset
     * HSION (disable HSI),
     * HSIDIVEN (disable 18MHz HSI division)
     * HSEON (disable HSE clock)
     * CSSHSEON (disable HSE clock monitoring)
     * PLLON (disable PLL)
     */
#ifdef STM32L0XX
    CLR(RCC->CR,
          RCC_CR_HSION | RCC_CR_HSIDIVEN | RCC_CR_HSEON |
          RCC_CR_CSSHSEON | RCC_CR_PLLON);
#else
    CLR(RCC->CR,
          RCC_CR_HSION | RCC_CR_HSEON |
          RCC_CR_PLLON);
#endif

    /*!< Disable all interrupts */
    RCC->CIER = 0x00000000;

    /* Vector Table Relocation in Internal FLASH */
    SCB->VTOR = FLASH_BASE;
}
