refactor tree, add ecad, mcad

This commit is contained in:
2019-08-28 23:23:48 -07:00
parent d5ddd76bef
commit ae837eef12
45 changed files with 4629 additions and 169 deletions

View File

@@ -26,8 +26,8 @@
namespace BSP {
using Common::ReturnCode;
using Common::time_t;
using BSP::ReturnCode;
using BSP::time_t;
RtcDriver::RtcSystemTimer RtcDriver::m_sys_timer;
@@ -106,11 +106,11 @@ ReturnCode RtcDriver::init_hw()
uint32_t time = 0;
SET(time, RTC_TR_PM);
SET_TO(time, RTC_TR_HT, 1 << RTC_TR_HT_Pos);
SET_TO(time, RTC_TR_HU, 2 << RTC_TR_HU_Pos);
SET_TO(time, RTC_TR_MNT, 5 << RTC_TR_MNT_Pos);
SET_TO(time, RTC_TR_HU, 0 << RTC_TR_HU_Pos);
SET_TO(time, RTC_TR_MNT, 0 << RTC_TR_MNT_Pos);
SET_TO(time, RTC_TR_MNU, 9 << RTC_TR_MNU_Pos);
SET_TO(time, RTC_TR_ST, 0 << RTC_TR_ST_Pos);
SET_TO(time, RTC_TR_SU, 0 << RTC_TR_SU_Pos);
SET_TO(time, RTC_TR_ST, 3 << RTC_TR_ST_Pos);
SET_TO(time, RTC_TR_SU, 6 << RTC_TR_SU_Pos);
RTC->TR = time;
CLR(RTC->ISR, RTC_ISR_INIT);
@@ -119,7 +119,7 @@ ReturnCode RtcDriver::init_hw()
SET(EXTI->EMR, EXTI_EMR_EM20);
SET(EXTI->RTSR, EXTI_RTSR_RT20);
// Enable Wakeup interrupts, we may/will use them later
// Enable Wakeup irq, we may/will use them later
SET(RTC->CR, RTC_CR_WUTIE);
NVIC_EnableIRQ(RTC_IRQn);
NVIC_SetPriority(RTC_IRQn, 0);
@@ -131,7 +131,7 @@ ReturnCode RtcDriver::init_hw()
return ReturnCode::OK;
}
ReturnCode RtcDriver::get_time(Common::WallClockTime &wall_time)
ReturnCode RtcDriver::get_time(BSP::WallClockTime &wall_time)
{
/*<! The value of TR in the shadow register is locked when SSR is
read (by the system timer), until the date register is read. We're
@@ -155,12 +155,12 @@ ReturnCode RtcDriver::get_time(Common::WallClockTime &wall_time)
hours += 12;
}
new (&wall_time) Common::WallClockTime(hours, minutes, seconds);
new (&wall_time) BSP::WallClockTime(hours, minutes, seconds);
return ReturnCode::OK;
}
ReturnCode RtcDriver::set_time(const Common::WallClockTime &wall_time)
ReturnCode RtcDriver::set_time(const BSP::WallClockTime &wall_time)
{
enable_rtc_write();
@@ -191,13 +191,13 @@ ReturnCode RtcDriver::set_time(const Common::WallClockTime &wall_time)
return ReturnCode::OK;
}
ReturnCode RtcDriver::set_wakeup_in(Common::time_t wakeup_delay)
ReturnCode RtcDriver::set_wakeup_in(BSP::time_t wakeup_delay)
{
/*<! 2^64 / (1000000 * 32768) / 60 / 60 / 24 / 365 = ~17.85 This
value will only overflow for wakeup_delays > 17.85 years, so
this is fine. */
uint64_t delay_cycles = Common::Time::to_micros(wakeup_delay) * LSE_CLOCK_FREQ /
Common::Time::MICROS_PER_SEC;
uint64_t delay_cycles = BSP::Time::to_micros(wakeup_delay) * LSE_CLOCK_FREQ /
BSP::Time::MICROS_PER_SEC;
enable_rtc_write();
@@ -244,25 +244,29 @@ ReturnCode RtcDriver::set_wakeup_in(Common::time_t wakeup_delay)
return ReturnCode::OK;
}
Common::time_t RtcDriver::RtcSystemTimer::get_time()
BSP::time_t RtcDriver::RtcSystemTimer::get_time()
{
uint32_t new_secs, old_secs, ssr, subsecond;
uint32_t new_secs, old_secs, ssr;
uint64_t new_timer_ticks, new_millis;
do {
__disable_irq();
old_secs = m_seconds;
ssr = RTC->SSR & 0xFFFF;
new_secs = m_seconds;
__enable_irq();
} while (new_secs != old_secs);
new_secs = new_secs * LSE_CLOCK_FREQ;
new_timer_ticks = (uint64_t) new_secs * LSE_CLOCK_FREQ;
/** SSR is a countdown register */
subsecond = (new_secs + LSE_CLOCK_FREQ - 1 - ssr) * Common::Time::MILLIS_PER_SEC / LSE_CLOCK_FREQ;
return Common::Time::millis(subsecond);
new_millis = (new_timer_ticks + LSE_CLOCK_FREQ - 1 - ssr) * BSP::Time::MILLIS_PER_SEC / LSE_CLOCK_FREQ;
return BSP::Time::millis(new_millis);
}
void RtcDriver::RtcSystemTimer::increment_seconds()
{
/** TODO: Atomic increment */
__disable_irq();
m_seconds++;
__enable_irq();
}
void RtcDriver::increment_seconds()
@@ -274,7 +278,7 @@ static uint32_t wakeup_alarms = 0;
extern "C" void RTC_IRQHandler()
{
// Clear the wakeup and alarm interrupts in the EXTI
// Clear the wakeup and alarm irq in the EXTI
SET(EXTI->PR, EXTI_PR_PIF20 | EXTI_PR_PIF17);
if (RTC->ISR & RTC_ISR_ALRAF) {