Initial commit
Add startup code for STM32L031K6, and blink two LEDs, one with CPU, and one with the LPTIM at 60Hz for the (to-be-implemented) Sharp display.
This commit is contained in:
320
stm32f030f4p6.S
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320
stm32f030f4p6.S
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/* File: startup_ARMCM0.S
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* Purpose: startup file for Cortex-M0 devices. Should use with
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* GCC for ARM Embedded Processors
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* Version: V2.01
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* Date: 12 June 2014
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*
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*/
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/* Copyright (c) 2011 - 2014 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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.syntax unified
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.arch armv6-m
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.section .stack
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.align 3
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#ifdef __STACK_SIZE
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.equ Stack_Size, __STACK_SIZE
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#else
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.equ Stack_Size, 0x00000400
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#endif
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.globl __StackTop
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.globl __StackLimit
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__StackLimit:
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.space Stack_Size
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.size __StackLimit, . - __StackLimit
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__StackTop:
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.size __StackTop, . - __StackTop
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.section .heap
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.align 3
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#ifdef __HEAP_SIZE
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.equ Heap_Size, __HEAP_SIZE
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#else
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.equ Heap_Size, 0x00000C00
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#endif
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.globl __HeapBase
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.globl __HeapLimit
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__HeapBase:
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.if Heap_Size
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.space Heap_Size
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.endif
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.size __HeapBase, . - __HeapBase
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__HeapLimit:
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.size __HeapLimit, . - __HeapLimit
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.section .vectors
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.align 2
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.globl __Vectors
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__Vectors:
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.long __StackTop /* Top of Stack */
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.long Reset_Handler /* Reset Handler */
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.long NMI_Handler /* NMI Handler */
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.long HardFault_Handler /* Hard Fault Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long SVC_Handler /* SVCall Handler */
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.long 0 /* Reserved */
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.long 0 /* Reserved */
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.long PendSV_Handler /* PendSV Handler */
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.long SysTick_Handler /* SysTick Handler */
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/* External interrupts */
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.long WDT_IRQHandler /* 0: Watchdog Timer */
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.long RTC_IRQHandler /* 1: Real Time Clock */
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.long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
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.long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
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.long MCIA_IRQHandler /* 4: MCIa */
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.long MCIB_IRQHandler /* 5: MCIb */
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.long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
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.long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
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.long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
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.long UART4_IRQHandler /* 9: UART4 - not connected */
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.long AACI_IRQHandler /* 10: AACI / AC97 */
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.long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
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.long ENET_IRQHandler /* 12: Ethernet */
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.long USBDC_IRQHandler /* 13: USB Device */
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.long USBHC_IRQHandler /* 14: USB Host Controller */
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.long CHLCD_IRQHandler /* 15: Character LCD */
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.long FLEXRAY_IRQHandler /* 16: Flexray */
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.long CAN_IRQHandler /* 17: CAN */
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.long LIN_IRQHandler /* 18: LIN */
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.long I2C_IRQHandler /* 19: I2C ADC/DAC */
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.long 0 /* 20: Reserved */
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.long 0 /* 21: Reserved */
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.long 0 /* 22: Reserved */
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.long 0 /* 23: Reserved */
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.long 0 /* 24: Reserved */
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.long 0 /* 25: Reserved */
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.long 0 /* 26: Reserved */
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.long 0 /* 27: Reserved */
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.long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
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.long 0 /* 29: Reserved - CPU FPGA */
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.long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
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.long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
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.size __Vectors, . - __Vectors
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.text
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.thumb
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.thumb_func
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.align 1
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.globl Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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/* Firstly it copies data from read only memory to RAM. There are two schemes
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* to copy. One can copy more than one sections. Another can only copy
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* one section. The former scheme needs more instructions and read-only
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* data to implement than the latter.
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* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
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#ifdef __STARTUP_COPY_MULTIPLE
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/* Multiple sections scheme.
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*
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* Between symbol address __copy_table_start__ and __copy_table_end__,
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* there are array of triplets, each of which specify:
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* offset 0: LMA of start of a section to copy from
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* offset 4: VMA of start of a section to copy to
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* offset 8: size of the section to copy. Must be multiply of 4
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r4, =__copy_table_start__
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ldr r5, =__copy_table_end__
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.L_loop0:
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cmp r4, r5
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bge .L_loop0_done
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ldr r1, [r4]
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ldr r2, [r4, #4]
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ldr r3, [r4, #8]
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.L_loop0_0:
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subs r3, #4
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blt .L_loop0_0_done
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ldr r0, [r1, r3]
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str r0, [r2, r3]
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b .L_loop0_0
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.L_loop0_0_done:
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adds r4, #12
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b .L_loop0
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.L_loop0_done:
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#else
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/* Single section scheme.
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*
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* The ranges of copy from/to are specified by following symbols
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* __etext: LMA of start of the section to copy from. Usually end of text
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* __data_start__: VMA of start of the section to copy to
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* __data_end__: VMA of end of the section to copy to
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*
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* All addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__etext
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ldr r2, =__data_start__
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ldr r3, =__data_end__
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subs r3, r2
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ble .L_loop1_done
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.L_loop1:
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subs r3, #4
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ldr r0, [r1,r3]
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str r0, [r2,r3]
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bgt .L_loop1
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.L_loop1_done:
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#endif /*__STARTUP_COPY_MULTIPLE */
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/* This part of work usually is done in C library startup code. Otherwise,
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* define this macro to enable it in this startup.
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*
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* There are two schemes too. One can clear multiple BSS sections. Another
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* can only clear one section. The former is more size expensive than the
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* latter.
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*
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* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
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* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
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*/
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#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
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/* Multiple sections scheme.
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*
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* Between symbol address __copy_table_start__ and __copy_table_end__,
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* there are array of tuples specifying:
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* offset 0: Start of a BSS section
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* offset 4: Size of this BSS section. Must be multiply of 4
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*/
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ldr r3, =__zero_table_start__
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ldr r4, =__zero_table_end__
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.L_loop2:
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cmp r3, r4
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bge .L_loop2_done
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ldr r1, [r3]
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ldr r2, [r3, #4]
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movs r0, 0
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.L_loop2_0:
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subs r2, #4
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blt .L_loop2_0_done
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str r0, [r1, r2]
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b .L_loop2_0
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.L_loop2_0_done:
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adds r3, #8
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b .L_loop2
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.L_loop2_done:
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#elif defined (__STARTUP_CLEAR_BSS)
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/* Single BSS section scheme.
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*
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* The BSS section is specified by following symbols
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* __bss_start__: start of the BSS section.
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* __bss_end__: end of the BSS section.
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*
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* Both addresses must be aligned to 4 bytes boundary.
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*/
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ldr r1, =__bss_start__
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ldr r2, =__bss_end__
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movs r0, 0
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subs r2, r1
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ble .L_loop3_done
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.L_loop3:
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subs r2, #4
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str r0, [r1, r2]
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bgt .L_loop3
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.L_loop3_done:
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#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
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#ifndef __NO_SYSTEM_INIT
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bl SystemInit
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#endif
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#ifndef __START
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#define __START _start
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#endif
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bl __START
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.pool
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.size Reset_Handler, . - Reset_Handler
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.align 1
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.thumb_func
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.weak Default_Handler
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.type Default_Handler, %function
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Default_Handler:
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b .
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.size Default_Handler, . - Default_Handler
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/* Macro to define default handlers. Default handler
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* will be weak symbol and just dead loops. They can be
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* overwritten by other handlers */
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.macro def_irq_handler handler_name
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.weak \handler_name
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.set \handler_name, Default_Handler
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.endm
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def_irq_handler NMI_Handler
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def_irq_handler HardFault_Handler
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def_irq_handler SVC_Handler
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def_irq_handler PendSV_Handler
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def_irq_handler SysTick_Handler
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def_irq_handler WDT_IRQHandler
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def_irq_handler RTC_IRQHandler
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def_irq_handler TIM0_IRQHandler
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def_irq_handler TIM2_IRQHandler
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def_irq_handler MCIA_IRQHandler
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def_irq_handler MCIB_IRQHandler
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def_irq_handler UART0_IRQHandler
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def_irq_handler UART1_IRQHandler
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def_irq_handler UART2_IRQHandler
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def_irq_handler UART3_IRQHandler
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def_irq_handler UART4_IRQHandler
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def_irq_handler AACI_IRQHandler
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def_irq_handler CLCD_IRQHandler
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def_irq_handler ENET_IRQHandler
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def_irq_handler USBDC_IRQHandler
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def_irq_handler USBHC_IRQHandler
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def_irq_handler CHLCD_IRQHandler
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def_irq_handler FLEXRAY_IRQHandler
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def_irq_handler CAN_IRQHandler
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def_irq_handler LIN_IRQHandler
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def_irq_handler I2C_IRQHandler
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def_irq_handler CPU_CLCD_IRQHandler
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def_irq_handler SPI_IRQHandler
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.end
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