103 lines
3.2 KiB
C++
103 lines
3.2 KiB
C++
/*
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* Copyright (C) 2019 Max Regan
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "Bsp/Drivers/LptimPwm.h"
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#include "Bsp/macros.h"
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namespace BSP {
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using BSP::ReturnCode;
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LptimPwm::LptimPwm(LPTIM_TypeDef *lptim)
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: m_lptim(lptim)
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{}
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void LptimPwm::init_lptim()
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{
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/* Enable LPTIM in APB1 */
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#if defined(STM32L0XX)
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SET(RCC->APB1ENR,
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RCC_APB1ENR_LPTIM1EN);
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#elif defined(STM32L4XX)
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SET(RCC->APB1ENR1,
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RCC_APB1ENR1_LPTIM1EN);
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#else
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#error "Unsupported family"
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#endif
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// Enable low-speed internal
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RCC->CSR |= RCC_CSR_LSION;
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while (!(RCC->CSR & RCC_CSR_LSIRDY)) {};
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/*!< Set the LSE clock to be the source of the LPTIM */
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SET_TO(RCC->CCIPR,
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RCC_CCIPR_LPTIM1SEL,
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RCC_CCIPR_LPTIM1SEL_0);
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/** Write CR CFGR and IER while LPTIM is disabled (LPTIM_CR_ENABLE not yet set) */
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/*!< Disable Interrupts (not needed, this is the default */
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LPTIM1->IER = 0;
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/*!< Reset
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* ENC (Disable encoder mode)
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* TIMOUT (disable timeout mode)
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* TRIGEN (Trigger count start with software only)
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* PRELOAD (Update ARR and CMP registers immediately after write)
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* CKSEL (LPTIM is not using an input clock)
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* COUNTMODE (LPTIM counter updated on every clock pulse)
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* TRGFLT (Do not debounce triggers)
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*/
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CLR(LPTIM1->CFGR,
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LPTIM_CFGR_ENC | LPTIM_CFGR_TIMOUT | LPTIM_CFGR_TRIGEN |
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LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_PRELOAD | LPTIM_CFGR_CKSEL |
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LPTIM_CFGR_COUNTMODE);
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/*!< Set
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* PRESC (Set prescaler to 128. Using 32kHz LSE as input, this should
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* correspond to 250Hz counting.
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*/
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CLR(LPTIM1->CFGR, LPTIM_CFGR_PRESC);
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SET(LPTIM1->CR, LPTIM_CR_ENABLE);
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/*!< Do not modify ARR and CMP until after ENABLE bit is set */
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/*!< Produce a 60Hz, signal with minimal "high" time. The display
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only needs 2us of "high" time on EXTCOMM, and it draws a fair
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amount of power. */
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LPTIM1->ARR = 0x4FF;
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LPTIM1->CMP = 0x4FE;
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while(!(LPTIM1->ISR & LPTIM_ISR_ARROK)) {}
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while(!(LPTIM1->ISR & LPTIM_ISR_CMPOK)) {}
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/*!< Enable and start the timer */
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SET(LPTIM1->CR, LPTIM_CR_CNTSTRT);
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}
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ReturnCode LptimPwm::init()
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{
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init_lptim();
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return ReturnCode::OK;
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}
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}
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