95 lines
3.1 KiB
C++
95 lines
3.1 KiB
C++
/*
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* Copyright (C) 2020 Max Regan
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "Bsp/macros.h"
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#include "Mcu.h"
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void SystemInit()
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{
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/**
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* Use the MSI for the system clock, and disable all other clocks.
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*/
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#if defined(STM32L0XX)
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// STM32L0
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SET_TO(RCC->ICSCR,
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RCC_ICSCR_MSIRANGE,
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RCC_ICSCR_MSIRANGE_6);
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#elif defined(STM32L4XX)
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// STM32L4
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SET_TO(RCC->CR,
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RCC_CR_MSIRANGE,
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RCC_CR_MSIRANGE_6);
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#else
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#error "Unsupported device type"
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#endif
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/*!< Set MSION bit. Set by hardware to force the MSI oscillator ON
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* when exiting from Stop or Standby mode, or in case of a failure
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* of the HSE oscillator used directly or indirectly as system
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* clock. This bit cannot be cleared if the MSI is used as system
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* clock. */
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SET(RCC->CR,
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RCC_CR_MSION);
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/*!< Set internal representation of clock frequency to 4MHz */
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// system_clk_freq = 4u << 22;
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/*!< Reset
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* SW[1:0] (use MSI oscillator as system clock),
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* HPRE[3:0] (do not divide AHB clock in prescaler) ,
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* PPRE1[2:0] (do not divide APB low-speed clock)
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* PPRE2[2:0] (do not divide APB high-speed clock),
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* MCOSEL[2:0] (disable MCO clock),
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* MCOPRE[2:0] (disable MCO prescaler) */
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CLR(RCC->CFGR,
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RCC_CFGR_SW | ~RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 |
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RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE);
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/*!< Reset HSEBYP bit (disable HSE bypass) */
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CLR(RCC->CR,
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RCC_CR_HSEBYP);
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/*!< Reset
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* HSION (disable HSI),
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* HSIDIVEN (disable 18MHz HSI division)
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* HSEON (disable HSE clock)
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* CSSHSEON (disable HSE clock monitoring)
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* PLLON (disable PLL)
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*/
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#ifdef STM32L0XX
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CLR(RCC->CR,
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RCC_CR_HSION | RCC_CR_HSIDIVEN | RCC_CR_HSEON |
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RCC_CR_CSSHSEON | RCC_CR_PLLON);
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#else
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CLR(RCC->CR,
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RCC_CR_HSION | RCC_CR_HSEON |
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RCC_CR_PLLON);
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#endif
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/*!< Disable all interrupts */
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RCC->CIER = 0x00000000;
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/* Vector Table Relocation in Internal FLASH */
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SCB->VTOR = FLASH_BASE;
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}
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