84 lines
2.4 KiB
C++
84 lines
2.4 KiB
C++
/*
|
|
* Copyright (C) 2019 Max Regan
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
|
* of this software and associated documentation files (the "Software"), to deal
|
|
* in the Software without restriction, including without limitation the rights
|
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
|
* copies of the Software, and to permit persons to whom the Software is
|
|
* furnished to do so, subject to the following conditions:
|
|
* The above copyright notice and this permission notice shall be included in
|
|
* all copies or substantial portions of the Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
|
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
|
* THE SOFTWARE.
|
|
*/
|
|
|
|
#include "Bsp/Drivers/SpiDriver.h"
|
|
#include "Bsp/macros.h"
|
|
|
|
namespace BSP {
|
|
|
|
using RC = BSP::ReturnCode;
|
|
using BSP::Schedule::TaskScheduler;
|
|
using BSP::Schedule::NextTime;
|
|
using BSP::GpioPin;
|
|
using BSP::Time;
|
|
|
|
SpiDriver::SpiDriver(TaskScheduler &scheduler, GpioPin &nss)
|
|
: m_scheduler(scheduler)
|
|
, m_spi(SPI1)
|
|
, m_nss(nss)
|
|
{}
|
|
|
|
void SpiDriver::init()
|
|
{
|
|
RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
|
|
|
|
// Enable Master mode and half the baud rate, so it's set to ~1MHz
|
|
m_spi->CR1 |= SPI_CR1_MSTR | SPI_CR1_LSBFIRST | SPI_CR1_SSM;
|
|
//m_spi->CR1 |= 1u << SPI_CR1_BR_Pos;
|
|
m_spi->CR2 |= SPI_CR2_SSOE;
|
|
}
|
|
|
|
NextTime SpiDriver::execute()
|
|
{
|
|
return NextTime::never();
|
|
}
|
|
|
|
RC SpiDriver::tx_blocking(const uint8_t *data, size_t len)
|
|
{
|
|
if (len <= 0) {
|
|
return RC::FAIL;
|
|
}
|
|
|
|
m_spi->CR1 |= SPI_CR1_SPE;
|
|
|
|
CLR(m_spi->CR1, SPI_CR1_SSI);
|
|
m_nss.write(1);
|
|
|
|
for (size_t i = 0; i < len; i++) {
|
|
while (!(m_spi->SR & SPI_SR_TXE)) {}
|
|
m_spi->DR = data[i];
|
|
}
|
|
|
|
while (!(m_spi->SR & SPI_SR_TXE)) {}
|
|
|
|
// Ensure that NSS is held for long enough to meet the display's thSCS
|
|
for (int i = 0; i < 4; i++);
|
|
|
|
m_spi->CR1 &= ~SPI_CR1_SPE;
|
|
SET(m_spi->CR1, SPI_CR1_SSI);
|
|
m_nss.write(0);
|
|
CLR(GPIOA->ODR, GPIO_ODR_OD4);
|
|
|
|
return RC::OK;
|
|
}
|
|
|
|
}
|